ddu18 8-tap, ecl-interfaced fixed delay line (series ddu18) d a ta delay devices, i n c. ? 3 features packages 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 gnd n/c t1 t2 t3 gnd gnd t4 t5 t6 t7 t8 in n/c n/c n/c n/c gnd vee n/c n/c n/c n/c gnd 24 19 18 13 1 3 4 5 6 7 8 9 10 11 12 gn d t1 t2 t3 gn d gn d t4 t5 t6 t7 t8 in gn d vee gn d ? eight equally spaced outputs ? fits in 400 mil 24-pin dip socket ? input & outputs fully 100k-ecl interfaced & buffered d d u 18-x x c 4 sm d ddu1 8 - x x m c4 m i l sm d ddu1 8 - x x di p d d u 1 8 - x x m m ilita r y d i p functional description the ddu18-series device is a 8-tap digitally buffered delay line. the signal input (in) is reproduced at the out puts (t1-t8), shifted in time by an amount determined by the device das h number (see table). for dash numbers less than 16, the total delay of the line is measured from t1 to t8. the nominal tap-to-tap delay incr ement is given by one-seventh of the total delay, and the inherent delay from in to t1 is nominally 2.0ns. for dash numbers greater than or equal to 16, the total delay of the line is measured from in to t8. the nominal tap-to-tap delay increment is given by one-eighth of this number. pin descriptions in signal input t1-t8 tap outputs vee -5 volts gnd ground dash number specifications part number total delay (ns) delay per tap (ns) ddu18-4 3.5 1.0 * 0.5 0.3 ddu18-8 7.0 1.0 * 1.0 0.4 ddu18-12 10.5 1.0 * 1.5 0.4 ddu18-16 16 1.0 2.0 0.5 ddu18-20 20 1.0 2.5 1.0 ddu18-24 24 1.2 3.0 1.5 ddu18-32 32 1.6 4.0 2.0 ddu18-40 40 2.0 5.0 2.0 ddu18-48 48 2.4 6.0 2.0 ddu18-56 56 2.8 7.0 2.0 ddu18-64 64 3.2 8.0 2.0 ddu18-72 72 3.6 9.0 2.0 ddu18-80 80 4.0 10.0 2.5 ddu18-100 100 5.0 12.5 2.5 ddu18-120 120 6.0 15.0 3.0 ddu18-160 160 8.0 20.0 4.0 ddu18-200 200 10.0 25.0 5.0 * total delay is referenced to first tap output input to first tap = 2.0ns 1ns note: a n y dash number betw een 4 and 200 not show n is also av ailable. series specifications ? minimum input pulse w i dth: 40% of total delay ? output rise time: 2ns typical ? supply v o ltage: -5vdc 5% ? pow e r dissipation: 500mw typical (no load) ? operating temperature: 0 to 85 c ? tem p . coefficient of total delay : 100 ppm/ c 1/ 7 1/ 7 1/ 7 1/ 7 vc c g n d in t1 t2 t3 t4 functi o nal di agra m for da sh num b ers < 1 6 2 . 0ns 1/ 7 1/ 7 1/ 7 t5 t6 t 7 t 8 1/ 8 1/ 8 1/ 8 1/ 8 vc c g n d in t1 t2 t3 t4 functi o nal di agra m for da sh num b ers >= 1 6 1/ 8 1/ 8 1/ 8 t5 t6 t 7 t 8 1/ 8 ? 2004 data delay dev i ces doc #97041 data delay devices, inc. 1 5/5/04 3 mt. prospect ave. clifton, nj 07013
ddu18 application notes high frequency response the ddu18 tolerances are guaranteed for input pulse widths and periods greater than those specified in the test conditions. although the device will function properly for pulse widths as small as 40% of the total delay and periods as small as 80% of the total delay (for a symmetric input), the delays may deviate from their values at low frequency. however, for a given input condition, the deviation will be repeatable from pulse to pulse. contact technical support at data delay devices if your application requires device testing at a specific input condition. power supply bypassing the ddu18 relies on a stable power supply to produce repeatable delays within the stated tolerances. a 0.1uf capac itor from vee to gnd, loc a ted as c l os e as pos s i ble to the vee pin, is recommended. a wide vee trace and a clean ground plane should be used. device specifications table 1: absolute maximum ratings p a r a m e t e r s y m b o l m i n m a x u n i t s n o t e s dc supply voltage v ee - 7 . 0 0 . 3 v input pin voltage v in v ee - 0.3 0.3 v storage temperature t st rg - 5 5 1 5 0 c lead temperature t lead 3 0 0 c 1 0 s e c table 2: dc electrical characteristics (0c to 85c) p a r a m e t e r s y m b o l m i n t y p m a x u n i t s n o t e s high level output voltage v oh - 1 . 0 2 5 - 0 . 8 8 0 v v ih = max,50 ? to -2v low level output voltage v ol - 1 . 8 1 0 - 1 . 6 2 0 v v il = mi n, 50 ? to -2v high level input voltage v ih - 1 . 1 6 5 - 0 . 8 8 0 v low level input voltage v il - 1 . 8 1 0 - 1 . 4 7 5 v high level input current i ih 3 4 0 a v ih = max low level input current i il 0 . 5 a v il = mi n doc #97041 data delay devices, inc. 2 5/5/04 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
ddu18 package dimensions 19 18 ddu18-xx (co m m e r c ial di p ) ddu18-xxm (m ilitar y di p ) . 130 . 030 1. 300 ma x . 14 6 . 300 ma x . . 018 t y p . . 530 ma x . . 400 ty p . . 012 t y p . 1. 100 t y p . . 015 ty p . . 100 t y p . 12 11 13 24 5 3 789 1 0 d d u 18-xxc 4 (c o m m e r c ial s m d ) ddu18-xxm c4 (m ilitar y s m d) 1. 280 . 020 . 882 . 005 . 020 t y p . . 040 t y p . . 100 . 090 1. 100 . 280 ma x . . 590 ma x . . 010 . 002 . 050 . 010 . 710 . 005 . 007 . 005 123456789 1 0 1 1 1 2 13 14 15 16 17 18 19 20 21 22 23 24 doc #97041 data delay devices, inc. 3 5/5/04 3 mt. prospect ave. clifton, nj 07013
ddu18 delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c load: 50 ? to -2v supply voltage (vcc): -5.0v 0.1v c load : 5pf 10% input pulse: standard 10kh ecl threshold: (v oh + v ol ) / 2 levels (rising & falling) source impedance: 50 ? max. rise/fall time: 2.0 ns max. (measured between 20% and 80%) pulse width: pw in = 1.5 x total delay period: per in = 10 x total delay note: the above conditions are for test only and do not in any way restrict the operation of the device. t1 out tr i g in re f tr i g t est s e t u p de v i ce unde r t est (d u t ) os ci l l o s c op e pu l s e ge ne ra t o r in t2 t3 t4 t5 t6 t7 t8 ti m i n g d i a g r a m f o r te s t i n g d ri se d fa ll per in pw in t ri s e t fal l 20% 20 % 50% 50 % 8 0 % 80% 50% 50% v ih v il v oh v ol in p u t si g n al out p ut si g n al doc #97041 data delay devices, inc. 4 5/5/04 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
|
